1. Field of the Invention
The present invention relates to an array substrate, and more particularly, to a method of fabricating an array substrate for a display device including a thin film transistor.
2. Discussion of the Related Art
With rapid development of information technologies, display devices for displaying a large amount of information have been promptly developed. More particularly, flat panel display (FPD) devices having a thin profile, light weight and low power consumption such as organic electroluminescent display (OLED) devices and liquid crystal display (LCD) devices have been actively pursued and replaced with cathode ray tube (CRT).
Among the liquid crystal display devices, active matrix type liquid crystal display devices, which include thin film transistors to control on/off of respective pixels, have been widely used because of their high resolution, color rendering capability and superiority in displaying moving images.
In addition, organic electroluminescent display devices have been recently spotlighted because they have many merits as follows: organic electroluminescent display devices have high brightness and low driving voltages; because they are self-luminous, the organic electroluminescent display devices have excellent contrast ratios and ultra thin thicknesses; the organic electroluminescent display devices have response time of several micro seconds, and there are advantages in displaying moving images; the organic electroluminescent display devices have wide viewing angles and are stable under low temperatures; since the organic electroluminescent display devices are driven by low voltage of direct current (DC) 5V to 15V, it is easy to design and manufacture driving circuits; and a manufacturing process of an organic electroluminescent display device is very simple because only deposition and encapsulation steps are required. In the organic electroluminescent display devices, active matrix type display devices also have been widely used because of their low power consumption, high definition and large-sized possibility.
The active matrix type liquid crystal display devices and the active matrix type organic electroluminescent display devices include an array substrate having thin film transistors as switching elements to control on/off of respective pixels.
FIG. 1 is a cross-sectional view of illustrating an array substrate for a liquid crystal display device or an organic electroluminescent display device according to the related art. FIG. 1 shows a pixel region including a thin film transistor.
In FIG. 1, a gate line (not shown) and a data line 33 are formed on a substrate 11 and cross each other to define a pixel region P. A gate electrode 15 is formed in a switching region TrA of the pixel region P. A gate insulating layer 18 is formed on the gate electrode 15, and a semiconductor layer 28, which includes an active layer 22 of intrinsic amorphous silicon and ohmic contact layers 26 of impurity-doped amorphous silicon, is formed on the gate insulating layer 18. Source and drain electrodes 36 and 38 are formed on the ohmic contact layers 26. The source and drain electrodes 36 and 38 are spaced apart from each other to correspond to the gate electrode 15. The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28 and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA constitute a thin film transistor Tr.
A passivation layer 42 is formed on the source and drain electrodes 36 and 38 and the exposed active layer 22. The passivation layer 42 has a drain contact hole 35 exposing the drain electrode 38. A pixel electrode 50 is formed on the passivation layer 42 in the pixel region P. The pixel electrode 50 contacts the drain electrode 38 through the drain contact hole 45. Here, a semiconductor pattern 29 is formed under the data line 33. The semiconductor pattern 29 has a double-layered structure including a first pattern 27 of the same material as the ohmic contact layers and a second pattern 23 of the same material as the active layer 22.
In the semiconductor layer 28 formed in the switching region TrA of the array substrate, the active layer 22 of intrinsic amorphous silicon has different thicknesses depending on the position. That is, a portion of the active layer 22 under the ohmic contact layers 26 has a first thickness t1, and a portion of the active layer 22 exposed by removing the ohmic contact layers 26 has a second thickness t2, which is thinner than the first thickness t1. The different thicknesses of the active layer 22 are caused by a manufacturing method, and this decreases characteristics of the thin film transistor Tr.
FIGS. 2A to 2E are cross-sectional views of illustrating an array substrate in processes of fabricating the same according to the related art. FIGS. 2A to 2E show the related art substrate in steps of forming a semiconductor layer and source and drain electrodes.
Although not shown in the figures, a gate line and a gate electrode are formed on a substrate 11 by depositing a metallic material and patterning it. The gate line extends along a first direction, and the gate electrode is connected to the gate line. A gate insulating layer is formed on the gate line and the gate electrode by depositing an inorganic insulating material.
Next, in FIG. 2A, an intrinsic amorphous silicon layer 20, an impurity-doped amorphous silicon layer 24 and a metal layer 30 are sequentially formed on the gate insulating layer. A photoresist layer (not shown) is formed on the metal layer 30 by applying photoresist. The photoresist layer is exposed to light through a mask and developed to form a first photoresist pattern 91 and a second photoresist pattern 92. The first photoresist pattern 91 corresponds to a region where the source and drain electrodes are formed and has a third thickness. The second photoresist pattern 92 corresponds to a region between the source and drain electrodes and has a fourth thickness, which is thinner than the third thickness.
In FIG. 2B, a source drain pattern 31, an impurity-doped amorphous silicon pattern 25 and an active layer 22 are formed by removing the metal layer 30 of FIG. 2A, which is exposed by the first and second photoresist patterns 91 and 92, and the impurity-doped amorphous silicon layer 24 of FIG. 2A and the intrinsic amorphous silicon layer 20 of FIG. 2A, which are disposed under the metal layer 30 of FIG. 2A.
In FIG. 2C, the second photoresist pattern 92 of FIG. 2B having the fourth thickness is removed by an ashing process. At this time, the first photoresist pattern 91 of FIG. 2B having the third thickness is partially removed to form a third photoresist pattern 93 having a reduced thickness on the source drain pattern 31.
In FIG. 2D, source and drain electrodes 36 and 38 are formed by removing the source drain pattern 31 of FIG. 2C exposed by the third photoresist pattern 93. The source and drain electrodes 36 and 38 are spaced apart from each other. At this time, the impurity-doped amorphous silicon pattern 25 is exposed between the source and drain electrodes 35 and 38.
In FIG. 2E, the impurity-doped amorphous silicon pattern 25 of FIG. 2D exposed between the source and drain electrodes 36 and 38 is dry-etched and removed, thereby forming ohmic contact layers 26 under the source and drain electrodes 36 and 38, respectively.
At this time, the impurity-doped amorphous silicon pattern 25 of FIG. 2D is over-etched. That is, dry-etching is performed for an enough time to completely remove the impurity-doped amorphous silicon pattern 25 of FIG. 2D between the source and drain electrodes 36 and 38, and the active layer 22 under the impurity-doped amorphous silicon pattern 25 of FIG. 2D is also partially removed by a predetermined thickness. Accordingly, the active layer 22 has different thicknesses t1 and t2 in a region under the ohmic contact layers 26 and a region between the source and drain electrodes 36 and 38. If the dry-etching is not performed for the enough time, the impurity-doped amorphous silicon pattern 25 of FIG. 2D remains on the active layer 22 between the source and drain electrodes 36 and 38. To prevent this, the dry-etching is performed for the enough time, and the active layer 22 between the source and drain electrodes 36 and 38 is partially removed.
Therefore, in the related art array substrate, the active layer 22 has different thicknesses, and this lowers the characteristics of the thin film transistor Tr of FIG. 1.
Meanwhile, the intrinsic amorphous silicon layer 20 of FIG. 2A may be deposited to have a thickness within a range of 1500 Å to 1800 Å considering the thickness of the active layer 22 removed during the dry-etching. Accordingly, the deposition time is increased, and the productivity is lowered.